1. Field of the Invention
The present invention generally relates to read only memory (ROM) devices and more particularly to an improved ROM device that includes complementary transistors which are programmed during manufacture by selective connection of the transistors to ground.
2. Description of the Related Art
Read only memory (ROM) array chips are well known in the art. The chips generally have a ROM array core, that includes a multiplicity of ROM cells, and a periphery formed of control elements controlling the operation of the array core. The ROM array stores programs and/or data in the form of bits, where a bit is either off (a logical value of 1) or on (a logical value of 0). Each bit is stored in a single cell, which is conventionally a single gate, n-channel transistor or ROM cell. A logical 1 is implemented with a transistor which has been shut off, such that it will not conduct when voltage is applied to it and a logical 0 is implemented with an active transistor which conducts when voltage is applied to it.
Further, conventional ROM cells utilize a reference bitline, that has a voltage between the precharge voltage (Vdd) and ground level, to decrease the size of the ROM array and to increase speed. If the ROM cell has a voltage above the reference voltage, it will represent a logical value of 1. If the ROM cell has a voltage below the reference voltage, it will represent a logical value of 0. However, the voltage difference between the high/low voltage and the reference voltage is narrow, which makes it difficult to identify the difference between a logical 1 and a logical 0. Further, each of these three bitline values (high, low, and reference) has a level of uncertainty based on bitline capacitance and bitline—bitline coupling. This uncertainty further reduces signal margin.
In order to save wiring levels, some conventional ROMs program the personality on the bitline side of the transistor. By doing this such designs can form the ROM utilizing only two metal levels. However, programming in this fashion causes the bitline capacitance to vary greatly depending on the ROM's personality. In the prior ROM design, the levels of uncertainty for signal margin were great enough that many “quieting grounds” had to be interspersed among the bitline to reduce bitline—bitline coupling. Such quieting grounds increase the size and decrease the speed of the array.
Therefore, there is a need for an improved ROM cell that avoids the disadvantages associated with single transistor ROM cells and which provides increased performance without substantially increasing the size or decreasing the speed of the ROM array. The invention described below provides such a structure.